1. Field of the Invention
The present invention pertains to the field of computer systems. More particularly, this invention relates to a processor for an upgradable multiprocessor computer system that provides an external indication of system bus ownership.
2. Background
Prior conventional computer systems typically include a single central processing unit. Typically, such a central processing unit is coupled to a system bus that provides communication to a variety of input/output devices. In such a computer system, the central processing unit typically fetches an instruction stream from a memory subsystem over the system bus and executes each instruction in the instruction stream. Such a central processing unit typically maintains a set of data structures in the memory subsystem and performs input/output accesses to the input/output devices over the system bus.
Such a prior single processor system usually implements an interrupt mechanism for handling external hardware exceptions in the system. For example, an input/output device controller in such a system typically causes a system interrupt to the central processing unit if an access is attempted to an input/output device that is in a powered down or a suspended state. The system interrupt indicates to the central processing unit that the input/output device requires exception handling. Typically, the system interrupt directs control of the central processing unit to an interrupt routine that restores power to the powered down or suspended input/output device. Thereafter, the central processing unit reissues the input/output access to the input/output device and continues normal execution.
Other prior computer systems may provide multiple central processing units to improve instruction execution performance. Each central processing unit in such a system is typically coupled to a system bus that provides communication to a memory subsystem and a set of input/output devices. Such a multiprocessor system usually yields improved instruction execution performance in comparison to a system having a single central processing unit because the instruction execution functions are shared among multiple central processing units.
Such a multiprocessor computer system typically provides mechanisms for sharing the external memory subsystem and the input/output devices coupled to the system bus among the multiple central processing units. For example, such a prior multiprocessor system usually implements a bus arbitration mechanism that enables each central processing unit to request and obtain access to the system bus.
Such a prior multiprocessor system also usually implements an interrupt mechanism for handling hardware exceptions in the system. In such a multiprocessor system, an access over the system bus that causes an exception may originate from any of the multiple central processing units coupled to the system bus. An input/output device controller in such a system typically directs a system interrupt to the central processing unit that originated the access that caused the exception.
Typically, an input/output device controller in such a system monitors the system bus and records ownership changes of the system bus between the multiple central processing units. Such an input/output device controller accordingly directs the system interrupt to the central processing unit that owned the system bus during the access that caused the exception. Unfortunately, such a prior system requires the implementation of relatively complex external hardware in the input/output device controller to monitor system bus ownership. Such complex hardware mechanisms usually increase the cost of such prior computer systems.
In addition, such mechanisms are impractical for a computer system that is upgradable from a single processor system to a multiple processor system. In such an upgradable system, a hardware mechanism for monitoring bus ownership and directing system interrupts would not be used if only one central processing unit is installed in the system. Moreover, the addition of such hardware to the system during upgrade would require extensive hardware modification to the system.